It's an interesting exploration. I at least got two things out of this:
1. That the two-pass assembler design from 6502 was only 2KB. Tricks from software like that tend to come in handy later on embedded systems.
2. His links on stepwise refinement of the Forth interpreter give a nice illustration of the concept. I rarely see an example that doesn't involve formal methods that turn most away or some useless objective.
So, mostly him having fun in his spare time. Yet, at least two reasons to keep a link to the project. Also, he ended up using the approach I keep suggesting here: port the Oberon System because it's simple and has plenty of features. He's doing that on Kesterel 3.
I'm planning on using a soft-core processor because FPGA dev boards are plentiful and relatively inexpensive. My plans are to await silicon from LowRISC project before considering real glass.
Sure, but he doesn't have to fund it himself, other groups have expressed an interest in creating a RISC-V ASIC, he could use one of those chips when it's ready.
Yeah, I know. I didn't expect the goal to be reasonable.
Nothing about the project is really all that reasonable, considering FPGAs are nearly entirely proprietary across the board, and because it'd be super expensive to make something that is actually truly open.
> "Nothing about the project is really all that reasonable, considering FPGAs are nearly entirely proprietary across the board, and because it'd be super expensive to make something that is actually truly open."
The Kestrel-4 plans to use the ICE-40 as one of its platforms, and at the time of writing this the ICE-40 FPGA family is the most open of all FPGA devices (fully open source development toolchain, etc...).
Did you see the specs? He went from a Commodore to a NUMA-scale machine that he will implement on a mix of Xilinx and ICE FPGA's. Not saying he can't do some fraction of it but those are some heavy specs.
After reading it again, you're all quite right, I was wrong, it's an April Fool's joke. Still, the principal of a computer on an ICE FPGA is a good one, even if it's not currently being pursued by this guy.
I'd like to try my hand at building my own iCE40-based motherboard for the Kestrel some day, but something like that would be at least two to three years into the future minimum, especially at my current rate of progress working solo. It's best to not have any expectations.
"Using Specware, we've specified and synthesized an entire computer. We even have flow charts of the hand movements of assdmbly line sorkers. The entire process, from design to manufacturing, should be correct by construction. As will be the computer."
He then added, "That's assuming the following assumptions are true. There's about 500 of them do bear with me on this PowerPoint..."
This project seems to be in a superposition of enormously ambitious project, light-years away from reaching the goal and elaborated joke. Does that sound about right? I really have a hard time telling from looking at the repository and I never heard of it before.
Depends on what you mean. If you're looking for a computer that can replace your daily driver, then yes it's years away from that. However, if you're looking for a new platform to explore and tinker with without needing FPGA knowledge, then it's close to that already.
Aha, I didn't understand that the kestrel 4 was an April fools joke? Blazemonger support? :) I was seriously dreaming about doing something similar but kestrel 3 is real afaics :)
Kestrel-3 is software emulation only at this point. However, after making some last minute touches to the system firmware (a dialect of eForth for both simplicity and hackability), I will switch over to working on Verilog. I already have video, keyboard, and GPIO cores written, so I only need to focus on the CPU.
I tried to port Oberon, but was not yet successful in getting the compiler fully debugged. I also need to finish the system image linker so I can generate bootable images. For this reason, I pushed ahead with putting Forth in firmware.
However, I do intend on completing Oberon at some point (or trying to solicit help in that area; porting OSes is most definitely NOT my strong suit). Instead of putting in ROM, though, it'll be bootable off of SD card.
No, it went out of stock after I'd put the site up. I'll remove the link (or find an alternative to something that describes what the Nexys-2 is) when I go to update docs.
I have not selected a replacement board yet (since my Nexys-2 still works fine, I intend on continuing to use it for the time being). If, after I post a complete set of Verilog sources, someone wants to try porting to the hardware of their choice, I'll be happy to include relevant links on the site. (Or until I change boards myself, whichever comes first.)
I mis-remembered. It's a monster from Rogue! I could swear I played some Rogue variant very long ago where it was spelled with an "a". Quick research shows that Rogue had it as "kestrel" since forever, though. These "hallucinatory monsters" ("bogusmon") seem like a new addition to Nethack.
Heh, I wondered if you were actually remembering such an esoteric fact about NetHack.
Looks like kestrel in NetHack dates back to version 3.1.0, released January 1993. The comment says "Rogue", so I'm sure it was done in tribute. They also added emu, xeroc, and venus flytrap as monster names from Rogue, used while the player is hallucinating.
1. That the two-pass assembler design from 6502 was only 2KB. Tricks from software like that tend to come in handy later on embedded systems.
2. His links on stepwise refinement of the Forth interpreter give a nice illustration of the concept. I rarely see an example that doesn't involve formal methods that turn most away or some useless objective.
So, mostly him having fun in his spare time. Yet, at least two reasons to keep a link to the project. Also, he ended up using the approach I keep suggesting here: port the Oberon System because it's simple and has plenty of features. He's doing that on Kesterel 3.