I had the same question, and it reminded me of a HN submission from roughly a year ago on a similar topic: The Talos II, Blackbird POWER9 systems support tagged memory[0]
>Nowadays, there is increasing interest in adding tagged memory functionality to CPU architectures. Such architectures associate one or more tag bits with each quantum of a system's memory. There are many motivations for this ability to associate “metadata” with individual memory words, but one of the most clear is the potential security benefits and the ability to track the providence of certain kinds of data in memory, such as pointers. This can be used to create capability-based architectures such as CHERI.
Based on that last sentence, one may reason that this MTE feature for ARM could be a basis for implementing CHERI on ARM.
>Nowadays, there is increasing interest in adding tagged memory functionality to CPU architectures. Such architectures associate one or more tag bits with each quantum of a system's memory. There are many motivations for this ability to associate “metadata” with individual memory words, but one of the most clear is the potential security benefits and the ability to track the providence of certain kinds of data in memory, such as pointers. This can be used to create capability-based architectures such as CHERI.
Based on that last sentence, one may reason that this MTE feature for ARM could be a basis for implementing CHERI on ARM.
[0] https://news.ycombinator.com/item?id=33381823