What is interesting to me is that it was easier to sling 20kA round the chip than to make a higher voltage power distribution bus and step down nearer the cores.
I guess this is a process limitation? i.e, the stuff you would need to make an appropriate step down isn't compatible with the other stuff they need?
1. Process limitations (no high voltage devices, poor analog characteristics, limited resistor choice, etc)
2. The skill set for power device/analog IC design is very different than digital design (and harder to recruit for as the talent base is relatively small).
3. On chip power converters universally suffer from poor inductor quality which trashes your efficiency (thus increasing cooling demands as well).
From a business perspective it would be quite risky and likely not cost effective.
TSMC 7nm has all the required stuff to build a DC-DC converter from 3V or 1.8V. Nobody would use on-chip inductors for high power DC-DC.
As for skillset, there are a bunch of IP companies with silicon proven designs available. I'm sure they didn't design their SERDES or PLL(s) in-house either.
Efficient DC-DC converters are area consuming due to high voltage devices abd the capacitors in general being very large. You would need SMD inductors on top of that. This means you used very precious silicon area for power delivery. It creates a lot of reliability headache since higher voltages cannot be routed closer to low-voltage stuff. If you're not crazy high in current consumption density (A/mm2) it doesn't make sense.
They also have another design advantage here. I believe they're not IO limited with their bumps.So they can use most of it for power, which is much better than any DC-DC solution.
I guess this is a process limitation? i.e, the stuff you would need to make an appropriate step down isn't compatible with the other stuff they need?