I asked about this yesterday [1], and I found this article[2]. I can't speak to the validity, but it appears that the 'distances' used in these marketing concepts are not the same distances that are used to measure things. I'm still curious what the actual controllable resolution of the feature sizes are in the '7nm process'. I get the feeling that it's more like 30nm, but the effective feature density is greater than yesterday because there is more control vertically, and diagonally, etc. and so they need a smaller number than yesterday. But still just ~30nm (not actually 7nm).
When Intel say they have 52nm wire pitch, this means that they produce wires that are 26nm wide, with 26nm distance between wires. Producing wires that are thinner, or that are closer together, is unreliable.
That said, they are probably able to position those wires at a higher precision. Without being involved in the manufacturing myself, I deduce this mainly from looking at optical proximity correction[1], for example, it's clear that the final masks used for production have more detail. Another indication is the fact that different masks seem to be aligned to basically nm-level precision (otherwise, the different parts of transistors and the vertical interconnects (vias) between wiring planes would not match up properly). The photographs one sees of the final product also indicate this. This means that the location of wires could theoretically be controlled very precisely, but for a mixture of wavelength and other (chemical? surface tension?) reasons, the size of the wires cannot be made smaller reliably.
I'd be curious to know how precise this alignment really is, and I've never seen numbers for it, but it must be incredibly precise. Given that a large part of it can be done optically, this is not even that surprising, compared to some of the other magic that's going on here.
